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pentium ? ii processor C low-power module datasheet product features the low-power module is a small, highly integrated assembly containing an intel pentium ? ii processor C low-power and its immediate system-level support. the processor module contains a power supply for the processors unique voltage requirements, a system level 2 cache memory, and the core logic required to bridge the processor to standard system buses. the module interfaces electrically to its host system via a 3.3-v pci bus, a 3.3-v memory bus and some control signals for the intel 443bx host bridge/controller. n pentium ? ii processor C low power running at 266 mhz n second-level cache of pipeline burst sram dedicated 64-bit wide bus for high speed data transfer 512 kbyte cache data array clock to bsram turns off when processor is in low-power states n processor core voltage regulation supports input voltages from 5 v to 21 v above 80 percent peak efficiency n active thermal feedback (atf) sensing internal a/d - digital signaling (smbus) across the module interface programmable trip point interrupt or poll mode for temperature reading n thermal transfer plate for heat dissipation n intel 443bx host bridge/controller dram controller supports edo and sdram at 3.3 v supports pci clkrun# protocol sdram clock enable support and self refresh of edo or sdram during suspend mode compatible smram (c_smram) and extended smram (e_smram) modes of power management; e_smram mode supports write-back cacheable smram up to 1 mbyte 3.3 v pci bus control, rev 2.1 compliant n support single agp-66 3.3 v device order number: 273256-001 june 1999
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? ii processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1999 *third-party brands and names are the property of their respective owners.
datasheet 3 pentium ? ii processor C low-power module contents 1.0 introduction .................................................................................................................. 7 1.1 module terminology.............................................................................................. 7 2.0 architecture overview ............................................................................................. 7 3.0 module connector interface ................................................................................10 3.1 signal definitions.................................................................................................10 3.1.1 signal list...............................................................................................10 3.1.2 memory (109 signals) ............................................................................11 3.1.3 agp (60 signals)................................................................................12 3.1.4 pci (58 signals) .................................................................................13 3.1.5 processor/piix4e sideband (8 signals).................................................14 3.1.6 power management/geyserville (11 signals) ........................................15 3.1.7 clock (9 signals) ....................................................................................16 3.1.8 voltages (54 signals) .............................................................................17 3.1.9 itp/jtag (9 signals) .............................................................................18 3.1.10 miscellaneous (82 signals) ....................................................................18 3.2 connector pin assignments ................................................................................19 3.3 pin and pad assignments ...................................................................................21 4.0 functional description ...........................................................................................23 4.1 low-power module..............................................................................................23 4.2 l2 cache .............................................................................................................23 4.3 443bx host bridge/controller .............................................................................23 4.3.1 memory organization .............................................................................24 4.3.2 reset strap options ...............................................................................24 4.3.3 pci interface ..........................................................................................25 4.3.4 agp interface.........................................................................................25 4.4 electrical requirements ......................................................................................25 4.4.1 dc requirements...................................................................................26 4.4.2 ac requirements ...................................................................................27 4.4.2.1 system bus clock (bclk) signal quality specifications and measurement guidelines ..........................................................28 4.5 module signal termination..................................................................................29 4.6 processor core voltage regulation ....................................................................29 4.6.1 voltage regulator efficiency ..................................................................29 4.6.2 voltage regulator control ......................................................................30 4.6.2.1 voltage signal definition and sequencing ................................30 4.6.3 power planes: bulk capacitance requirements ....................................32 4.6.4 surge current study...............................................................................32 4.6.4.1 slew-rate control: circuit description ......................................34 4.6.4.2 under-voltage lockout: circuit description ..............................36 4.6.4.3 over voltage lockout: circuit description.................................36 4.6.4.4 over current protection: circuit description .............................36 4.7 active thermal feedback....................................................................................37 4.8 power management ............................................................................................37 4.8.1 clock control architecture......................................................................37
pentium ? ii processor C low-power module 4 datasheet 4.8.2 normal state .......................................................................................... 39 4.8.3 auto halt state ....................................................................................... 39 4.8.4 stop grant state .................................................................................... 40 4.8.4.1 quick start state ....................................................................... 40 4.8.5 halt/grant snoop state.................................................................... 41 4.8.6 sleep state............................................................................................. 41 4.8.7 deep sleep state ................................................................................... 41 4.8.8 currently supported clock states .......................................................... 42 4.8.9 operating system implications of the quick start and sleep states ..... 42 4.9 typical pos/str power..................................................................................... 42 5.0 mechanical requirements .................................................................................... 43 5.1 module dimensions............................................................................................. 43 5.1.1 board area ............................................................................................. 43 5.1.2 module pin 1 location............................................................................ 44 5.1.3 printed circuit board thickness ............................................................. 45 5.1.4 height restrictions ................................................................................. 45 5.2 thermal transfer plate ....................................................................................... 46 5.3 module physical support .................................................................................... 47 5.3.1 module mounting requirements ............................................................ 47 5.3.1.1 module weight .......................................................................... 48 6.0 thermal specifications .......................................................................................... 49 7.0 labeling information ............................................................................................... 49 7.1 product tracking code ....................................................................................... 49 7.1.1 module identification bits ....................................................................... 50 8.0 environmental standards ..................................................................................... 50 figures 1 block diagram of the pentium ii processor C low-power module........................ 9 2 400-pin connector footprint pad numbers, module secondary side................ 22 3 bclk, tck, picclk generic clock waveform at the processor core pins...... 28 4 power on sequence timing ............................................................................... 31 5 instantaneous in-rush current model ................................................................ 33 6 instantaneous in-rush current ........................................................................... 33 7 over current protection circuit ........................................................................... 34 8 spice simulation using in rush protection......................................................... 35 9pentium ? ii processor C low power clock control states ................................. 38 10 low-power module board dimensions ............................................................... 43 11 low-power module board dimensions connector pin 1 orientation ............. 44 12 pcb board thickness ......................................................................................... 44 13 module mechanical drawing ............................................................................... 45 14 thermal transfer plate ....................................................................................... 46 15 thermal transfer plate ....................................................................................... 47 16 standoff holes, board edge clearance and emi containment ring .................. 48 17 module product tracking information ................................................................. 49
datasheet 5 pentium ? ii processor C low-power module tables 1 module connector signal summary....................................................................10 2 memory signal descriptions................................................................................11 3 agp signal descriptions .....................................................................................12 4 pci signal descriptions.......................................................................................13 5 processor/piix4e sideband signal descriptions ................................................14 6 power management/geyserville signal descriptions..........................................15 7 clock signal descriptions....................................................................................16 8 voltage descriptions ...........................................................................................17 9 itp/jtag pins.....................................................................................................18 10 miscellaneous pins..............................................................................................18 11 connector pin assignments, row a through row e .........................................19 12 connector pin assignments, row f through row k..........................................20 13 connector specifications.....................................................................................22 14 configuration straps for the 443bx host bridge/controller ................................24 15 power supply design specifications...................................................................26 16 module ac specifications (bclk) at the processor core pins...........................27 17 bclk signal quality specifications for simulation at the processor core..........28 18 typical voltage regulator efficiency...................................................................29 19 voltage signal definitions and sequences .........................................................30 20 capacitance requirement per power plane.......................................................32 21 thermal sensor smbus address.......................................................................37 22 new pins in the pentium ? ii processor C low power.........................................37 23 processor clock state characteristics ................................................................39 24 low-power clock states supported by processor..............................................42 25 low-power module power specifications ...........................................................49 26 environmental standards ....................................................................................50
pentium ? ii processor C low-power module 6 datasheet revision history revision date description 001 5/99 first publication of this document.
pentium ? ii processor C low-power module datasheet 7 1.0 introduction the pentium ? ii processor C low-power module is a fundamental building block for a system manufacturer to incorporate into a system. the pentium ii processor C low-power module incorporates a pentium ii processor Clow power core, second-level cache with tag ram, intel 443bx host bridge/controller (northbridge), voltage regulator, and an smbus thermal sensor on a single printed circuit board. intels host bridge architecture allows for physical partitioning at the pci, agp and dram interfaces; therefore the electrical interconnect defined for the module includes the pci bus, agp bus, dram memory bus and some host bridge sideband signals. an onboard voltage regulator provides the dc conversion from the system manufacturers system dc voltage to the processors core and i/o voltage. this isolation of the processor voltage requirements allows the system manufacturer to incorporate low-power modules with different processor variants into a single system. building around this modular design gives the system manufacturer these advantages: ? avoids complexities associated with designing high-speed processor core logic boards ? provides an upgrade path from previous modules for designs using a standard interface this document provides the technical information required to assist the oem in developing the latest systems for the applied computing market segment. 1.1 module terminology the following terms are used often in this document and are explained here for clarification: pentium ii processor C low power the central processing unit including cache components. processor core the processors execution engine. thermal transfer plate (ttp) the surface used by the oem to attach a system level thermal solution to the pentium ii processor C low-power module. thermal design power (tdp) the typical power consumed by the cpu while executing a standard application. 2.0 architecture overview the pentium ii processor C low-power module is a small, highly integrated assembly containing the pentium ii processor Clow power core with internal/bus frequencies of 266/66 mhz and its immediate system-level support. the module interfaces electrically to its host system via a 3.3 v pci bus, a 3.3 v agp bus, a 3.3 v memory bus and the intel 443bx host bridge/controller. the module includes a second-level cache of pipeline burst sram supporting up to 512 kbytes. the zz snooze mode power management featured in previous modules is not supported. instead it supports the stop clock mode of power management for the l2 srams. in this mode, the clock signals to the l2 srams are stopped or parked in a low power state by the processor.
pentium ? ii processor C low-power module 8 datasheet the module contains key features of the intel 443bx host bridge/controller. the dram controller supports edo at 3.3 v with a burst read at 7-2-2-2 (60 ns) or sdram at 3.3 v with a burst read at 8-1-1-1 (66 mhz, cl=2). the system controller provides a pci clkrun# signal to request piix4e to start or maintain the pci clock on the pci bus. the 82443bx clock enable support enables self refresh mode of edo or sdram during suspend mode and is compatible with smram (c_smram) and extended smram (e_smram) modes of power management; e_smram mode supports write-back cacheable smram up to 1 mbyte. the intel 443bx host bridge/controller is a 3.3 v pci bus control which is compliant with pci rev 2.1 specifications. the 443bx host bridge/controller is one of two physical vlsi devices that constitute the intel 440bx agpset. the second device (southbridge) is known as the piix4e pci/isa bridge. the system manufacturers system electronics, which connect to the module, must include a piix4e device. the piix4e provides extensive power management capabilities and is designed to support the 82443bx in the module. the processor core voltage regulation supports input voltages from 5 v to 21 v, enabling an above 80 percent peak efficiency. the regulator decouples processor voltage requirements from the system. the module incorporates active thermal feedback (atf) sensing compliant to the acpi rev 1.0 specification. this is accomplished by including an smbus compliant thermal sensor capable of supporting internal and external temperature sensing with programmable trip points. a thermal transfer plate for heat dissipation from the processor and 443bx provides a standard thermal attach point to which the system manufacturer connects a system thermal solution. figure 1 illustrates the block diagram of the pentium ii processor C low-power module.
pentium ? ii processor C low-power module datasheet 9 figure 1. block diagram of the pentium ii processor C low-power module 400 pin board-to-board connector cpu volt. reg. 5v-21v processor core voltage pci bus memory bus pclk1 443bx "northbridge" v_3 hclk0 piix4 sidebands atf sense smbus fsb pentium ? ii processor C low power core pb sram v_3s tag v_3s pb sram v_3s 2.5v backside bus i/o voltage r_gtl dclkwr dclkrd bsb agp bus gclki gclko smbus dclko
pentium ? ii processor C low-power module 10 datasheet 3.0 module connector interface 3.1 signal definitions table 1 provides a list of signals by category and the corresponding number of signals in each category. for proper signal termination, see the pentium ? ii processor C low power module at 266 mhz design guide (order number 273212). 3.1.1 signal list the following notations are used to denote the signal type: table 1. module connector signal summary signal group number memory 109 agp 60 pci 58 processor/piix4e sideband 8 power management/geyserville 11 clocks 9 voltage: v_dc 20 voltage: v_3s 9 voltage: v_5 3 voltage: v_3 16 voltage: vccagp 4 voltage: v_cpupu 1 voltage: v_clk 1 itp/jtag 9 module id 4 ground 45 reserved 33 total pins 400 i input pin o output pin o d open drain output pin. this pin requires a pull-up resistor. i d open drain input pin. this pin requires a pull-up resistor. i/o d input / open drain output pin. this pin requires a pull-up resistor. i/o bidirectional input/output pin
pentium ? ii processor C low-power module datasheet 11 the signal description also includes the type of buffer used for a particular signal: 3.1.2 memory (109 signals) table 2 lists the pentium ii processor C low-power module memory interface signals. gtl+ open drain gtl+ interface signal pci pci bus interface signals agp agp interface signals cmos the pentium ii processor C low-power module has low voltage ttl compatible (lvttl) interfacing. table 2. memory signal descriptions name type voltage description mecc[7:0] i/o cmos v_3 memory ecc data: these signals carry memory ecc data during access to dram. these pins are implemented by design but not tested on the module. rasa[5:0]# or csa[5:0]# o cmos v_3 row address strobe (edo): these pins select the dram row. chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. casa[7:0]# or dqma[7:0] o cmos v_3 column address strobe (edo): these pins select the dram column. input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. 1 mab[9:0]# mab[10] mab[12:11]# mab[13] o cmos v_3 memory address (edo/sdram): this is the row and column address for dram. the 443bx host bridge/controller has two identical sets of address lines (maa and mab#). the module supports only the mab set of address lines. for additional addressing features, please refer to the intel 440bx agpset datasheet (order number 290633). 2 mwea# o cmos v_3 memory write enable (edo/sdram): mwea# should be used as the write enable for the memory data bus. srasa# o cmos v_3 sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. this signal also allows row access and pre-charge. scasa# o cmos v_3 sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. this signal also allows column access. cke[5:0] o cmos v_3 sdram clock enable (sdram): sdram clock enable pin. when these signals are de-asserted, sdram enters power-down mode. each row is individually controlled by its own clock enable. md[63:0] i/o cmos v_3 memory data: these signals are connected to the dram data bus. they are not terminated on the module. notes: 1. dqma signals are non-inverted now. please refer to the 82443bx spec update. 2. mab[13] is a non-inverted address signal now. please refer to 82443bx spec update.
pentium ? ii processor C low-power module 12 datasheet 3.1.3 agp (60 signals) table 3 lists the pentium ii processor C low-power modules agp interface signals. table 3. agp signal descriptions (sheet 1 of 2) name type voltag e description gad[31:0] i/o agp v_3 agp address/data: the standard agp address and data lines. this bus functions in the same way as the pci ad[31:0] bus. the address is driven with frame# assertion, and data is driven or received in following clocks. gc/be[3:0]# i/o agp v_3 agp command/byte enable: this bus carries the command information during agp cycles when pipe# is being used. during an agp write, this bus contains byte enable information. the command is driven with frame# assertion, and byte enables corresponding to supplied or requested data are driven on the following clocks. gframe# i/o agp v_3 agp frame: not used during agp transactions. remains de- asserted by an internal pullup resistor. assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. gdevsel# i/o agp v_3 agp device select: same function as pci devsel#. not used during agp transactions. this signal is driven by the 443bx host bridge/controller when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. girdy# i/o agp v_3 agp initiator ready: indicates the agp compliant target is ready to provide all write data for the current transaction. asserted when the initiator is ready for a data transfer. gtrdy# i/o agp v_3 agp target ready: indicates the agp compliant master is ready to provide all write data for the current transaction. asserted when the target is ready for a data transfer. gstop# i/o agp v_3 agp stop: same function as pci stop#. not used during agp transactions. asserted by the target to request the master to stop the current transaction. greq# i agp v_3 agp request: agp master requests for agp. ggnt# o agp v_3 agp grant: same function as on pci. additional information is provided on the st[2:0] bus. pci grant: permission is given to the master to use pci. gpar i/o agp v_3 agp parity: a single parity bit is provided over gad[31:0] and gc/be[3:0]. this signal is not used during agp transactions. pipe# i agp v_3 pipelined request: asserted by the current master to indicate a full width address is to be queued by the target. the master queues one request each rising clock edge while pipe# is asserted. sba[7:0] i agp v_3 sideband address: this bus provides an additional conduit to pass address and commands to the 443bx host bridge/controller from the agp master. rbf# i agp v_3 read buffer full: indicates if the master is ready to accept previously requested low priority read data.
pentium ? ii processor C low-power module datasheet 13 3.1.4 pci (58 signals) table 4 lists the pentium ii processor C low-power modules pci interface signals. st[2:0] o agp v_3 status bus: provides information from the arbiter to a agp master on what it may do. these bits only have meaning when ggnt is asserted. adstb[b:a] i/o agp v_3 ad bus strobes: provide timing for double clocked data on the gad bus. the agent that is providing data drives these signals. these are identical copies of each other. sbstb i agp v_3 sideband strobe: provides timing for a side-band bus. it is always driven by the agent driving sba[7:0], i.e., by the agp master. table 3. agp signal descriptions (sheet 2 of 2) name type voltag e description table 4. pci signal descriptions (sheet 1 of 2) name type voltage description ad[31:0] i/o pci v_3 address/data: the standard pci address and data lines. the address is driven with frame# assertion, and data is driven or received in following clocks. c/be[3:0]# i/o pci v_3 command/byte enable: the command is driven with frame# assertion, and byte enables corresponding to supplied or requested data are driven on the following clocks. frame# i/o pci v_3 frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfers are desired by the cycle initiator. devsel# i/o pci v_3 device select: this signal is driven by the 443bx host bridge/controller when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o pci v_3 initiator ready: asserted when the initiator is ready for data transfer. trdy# i/o pci v_3 target ready: asserted when the target is ready for a data transfer. stop# i/o pci v_3 stop: asserted by the target to request the master to stop the current transaction. plock# i/o pci v_3 lock: indicates an exclusive bus operation and may require multiple transactions to complete. when lock# is asserted, non- exclusive transactions may proceed. the 443bx supports lock for processor initiated cycles only. pci initiated locked cycles are not supported req[4:0]# i pci v_3 pci request: pci master requests for pci. gnt[4:0]# o pci v_3 pci grant: permission is given to the master to use pci.
pentium ? ii processor C low-power module 14 datasheet 3.1.5 processor/piix4e sideband (8 signals) table 5 lists the modules processor and piix4e sideband signals at the connector interface. the voltage level for these signals is determined by v_cpupu, which is supplied by the module. phold# i pci v_3 pci hold: this signal comes from the expansion bridge; it is the bridge request for pci. the 443bx host bridge drains the dram write buffers, drains the processor-to-pci posting buffers, and acquires the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. phlda# o pci v_3 pci hold acknowledge: this signal is driven by the 443bx host bridge to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o pci v_3 parity: a single parity bit is provided over ad[31:0] and c/be[3:0]# serr# i/o pci v_3 system error: the 443bx asserts this signal to indicate an error condition. please refer to the intel 440bx agpset datasheet (order number 290633) for further information. clkrun# i/o d pci v_3 clock run: an open-drain output and also an input. the 443bx host bridge requests the central resource (piix4e) to start or maintain the pci clock by asserting clkrun#. the 443bx host bridge three-states clkrun# upon deassertion of reset (since clk is running upon deassertion of reset). pci_rst# i cmos v_3 reset: when asserted, this signal asynchronously resets the 443bx host bridge. the pci signals also three-state, compliant with pci rev 2.1 specifications. table 4. pci signal descriptions (sheet 2 of 2) name type voltage description table 5. processor/piix4e sideband signal descriptions (sheet 1 of 2) name type voltage description ferr# o cmos v_cpupu numeric coprocessor error: this pin functions as a ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is driven by the processor to the piix4e. ignne# i d cmos v_cpupu ignore error: this open drain signal is connected to the ignore error pin on the processor and is driven by the piix4e. init# i d cmos v_cpupu initialization: init# is asserted by the piix4e to the processor for system initialization. this signal is an open drain. intr i d cmos v_cpupu processor interrupt: intr is driven by the piix4e to signal the processor that an interrupt request is pending and needs to be serviced. this signal is an open drain. nmi i d cmos v_cpupu non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the piix4e isa bridge generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. this signal is an open drain.
pentium ? ii processor C low-power module datasheet 15 3.1.6 power management/geyserville (11 signals) table 6 lists the modules power management signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermal sensor thermal sensor, there are reserved serial addresses for future use. see active thermal feedback on page 37 for more details. a20m# i d cmos v_cpupu address bit 20 mask: when enabled, this open drain signal causes the processor to emulate the address wraparound at one mbyte which occurs on the intel 8086 processor. smi# i d cmos v_cpupu system management interrupt: smi# is an active low synchronous output from the piix4e that is asserted in response to one of many enabled hardware or software events. the smi# open drain signal can be an asynchronous input to the processor. however, in this chip set smi# is synchronous to pclk. stpclk# i d cmos v_cpupu stop clock: stpclk# is an active low synchronous open drain output from the piix4e that is asserted in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pciclk. when the processor samples stpclk# asserted it responds by entering a low power state (quick start). the processor will only exit this mode when this signal is de-asserted. table 5. processor/piix4e sideband signal descriptions (sheet 2 of 2) name type voltage description table 6. power management/geyserville signal descriptions (sheet 1 of 2) name type voltage description sus_stat1# i cmos v_3always ? suspend status: this signal connects to the sus_stat1# output of piix4e. it provides information on host clock status and is asserted during all suspend states. vr_on i cmos v_3s vr_on: voltage regulator on. this 3.3 v (5 v tolerant) signal controls the operation of the modules voltage regulator. vr_on should be generated as a function of the piix4e susb# signal which is used for controlling the suspend state b voltage planes. vr_pwrgd o v_3s vr_pwrgd: this signal is driven high by the to indicate the voltage regulator is stable and is pulled low using a 131.6k resistor when inactive. it can be used in some combination to generate the system pwrgood signal. bxpwrok i cmos v_3 power ok to bx: this signal must go active 1ms after the v_3 power rail is stable. sm_clk i/o d cmos v_3 serial clock: this clock signal is used on the smbus interface to the digital thermal sensor. sm_data i/o d cmos v_3 serial data: open-drain data signal on the smbus interface to the digital thermal sensor. atf_int# o d cmos v_3 atf interrupt: this signal is an open-drain output signal of the digital thermal sensor. ? v_3always: 3.3 v voltage supply. it is generated whenever v_dc is available and supplied to the piix4e resume well.
pentium ? ii processor C low-power module 16 datasheet 3.1.7 clock (9 signals) table 7 lists the modules clock signals. g_sus_stat1# i cmos v_3 g_sus_stat1#: the sus_stst1# signal gated by the geyserville control logic. g_sus_stat1# should be used in place of the sus_stat1# signal in the system electronics design. this signal is not implemented on the current module, and is defined for future upgrade ability purposes only. g_lo/hi# i cmos v_3 new signal from a piix4e gpio pin that defines entry into a geyserville state change to the geyserville control logic. this signal is not implemented on the current module, and is defined for future upgrade ability purposes only. g_cpu_stp# i cmos v_3 the cpu_stp# signal gated by the geyserville control logic. this signal is not implemented on the current module, and is defined for future upgrade ability purposes only. vrchgng# o cmos v_3 a geyserville control logic signal that indicates that the actual state change is in progress. the vr setpoint has changed and the vr is settling. when this signal de- asserts, the new state is sent to the processor. system electronics use this signal to generate an sci to force a transition out of deep sleep. this signal is not implemented on the current module, and is defined for future upgrade ability purposes only. table 6. power management/geyserville signal descriptions (sheet 2 of 2) name type voltage description ? v_3always: 3.3 v voltage supply. it is generated whenever v_dc is available and supplied to the piix4e resume well. table 7. clock signal descriptions (sheet 1 of 2) name type voltage description pclk i pci v_3s pci clock in: pclk is an input to the module is one of the systems pci clocks. this clock is used by all of the 443bx host bridge logic in the pci clock domain. this clock is stopped when the piix4e pci_stp# signal is asserted and/or during all suspend states. hclk[1:0] i cmos v_clk host clock in: only hclk0 is an input to the module from the ck100-m clock source and is used by the processor and 443bx host bridge/controller. hclk0 is the only clock input supplied to the module. this clock is stopped when the piix4e cpu_stp# signal is asserted and/or during all suspend states. dclko o cmos v_3 sdram clock out: 66 mhz sdram clock reference generated internally by the 443bx host bridge/controller onboard pll. it feeds an external buffer that produces multiple copies for the sodimms. dclkrd i cmos v_3 sdram read clock: feedback reference from the sdram clock buffer. this clock is used by the 443bx host bridge/controller when reading data from the sdram array. dclkwr i cmos v_3 sdram write clock: feedback reference from the sdram clock buffer. this clock is used by the 443bx host bridge/controller when writing data to the sdram array.
pentium ? ii processor C low-power module datasheet 17 3.1.8 voltages (54 signals) table 8 lists the modules voltage signal definitions. gclkin i cmos v_3 agp clock in: the gclkin input is a feedback reference from the gclko signal. gclko o cmos v_3 agp clock out: this signal is generated by the 443bx host bridge/controller onboard pll from the hclk0 host clock reference. the frequency of gclko is 66 mhz. the gclko output is used to feed both the pll reference input pin on the 443bx host bridge/controller and the agp device. the board layout must maintain complete symmetry on loading and trace geometry to minimize agp clock skew. fqs o cmos v_3s frequency select: this output signal provides the status of the host clock frequency to the system electronics. this signal is static and is pulled either low or high to the v_clk voltage supply through a 10-k w resistor. this module is designed for the 66-mhz strapping option shown below. fqs=0 indicates 66 mhz fqs=1 indicates 100 mhz (for future modules) table 7. clock signal descriptions (sheet 2 of 2) name type voltage description table 8. voltage descriptions name type number description v_dc i 20 dc input: 5 - 21 v v_3s i 9 susb# controlled 3.3 v: power-managed 3.3 v voltage supply. an output of the voltage regulator on the system electronics. this rail is off during str, std, and soff. v_5 i 3 susc# controlled 5 v: power-managed 5 v voltage supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_3 i 16 susc# controlled 3.3 v: power-managed 3.3 v voltage supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. vccagp i 4 agp i/o voltage: for this revision of the module, this rail must be connected to v_3. v_cpupu o 1 processor i/o ring: driven by the module to power processor interface signals such as the piix4e open-drain pullups for the processor/piix4e sideband signals. v_clk o 1 processor clock rail: driven by the module to power the ck100-m vddcpu rail.
pentium ? ii processor C low-power module 18 datasheet 3.1.9 itp/jtag (9 signals) table 9 lists the modules itp/jtag signals, which the system electronics can use to implement a jtag chain and itp port, if desired. 3.1.10 miscellaneous (82 signals) table 10 lists the modules miscellaneous signal pins. table 9. itp/jtag pins name type voltage description tdo o v_cpupu jtag test data out: serial output port. tap instructions and data are shifted out of the processor from this port. tdi i v_cpupu jtag test data in: serial input port. tap instructions and data are shifted into the processor from this port. tms i v_cpupu jtag test mode select: controls the tap controller change sequence. tclk i v_cpupu jtag test clock: testability clock for clocking the jtag boundary scan sequence. trst# i v_cpupu jtag test reset: asynchronously resets the tap controller in the processor. fs_reset# o gtl+ processor reset: processor reset status to the itp. vtt o v_core gtl+ termination voltage: used by the poweron pin on the itp debug port to determine when target system is on. poweron pin is pulled up using a 1 k w resistor to vtt. fs_preq# i v_cpupu debug mode request: driven by the itp - makes request to enter debug mode. fs_prdy# o gtl+ debug mode ready: driven by the processor - informs the itp that the processor is in debug mode. note: recommendation: dbrest# (reset target system) on the itp debug port can be logically anded with the signal vr_pwrgd and connected to the piix4e input pwrok. table 10. miscellaneous pins name type number description module id[3:0] o cmos 4 module revision id: these pins track the revision level of the processor module. a 100 k w pull up resistor to v_3s is required on these signals and to be placed on the system electronics for these signals. ground i 45 ground reserved rsvd 33 unallocated reserved pins and should not be connected.
pentium ? ii processor C low-power module datasheet 19 3.2 connector pin assignments table 11 and table 12 list the signals for each pin of the connector from the module to the system electronics. refer to pin and pad assignments on page 21 for the pin assignments of the pads on the connector. table 11. connector pin assignments, row a through row e (sheet 1 of 2) pin# row a row b row c row d row e 1 sba5 adstbb gnd gad31 sba7 2 gad25 gad24 sba6 sba4 sba0 3 gad30 gad29 gad26 gad27 gnd 4 gnd vccagp gad4 gad6 gad8 5 rbf# gad1 gad3 gad5 gc/be0# 6 bxpwrok reserved gad2 adstba gnd 7 md0 md1 v_3 clkrun# gad7 8 md2 md33 gnd md32 gad0 9 md36 md4 md3 md35 md34 10 md7 md38 md37 md6 md5 11 md41 md42 md40 md39 md8 12 md43 md11 gnd md10 md9 13 md14 md45 md44 md13 md12 14 mecc4 mecc0 md15 md47 md46 15 scasa# wea# mecc5 reserved gnd 16 gnd mid1 dqma0 dqma1 reserved 17 v_3 dqma4 mid0 dqma5 csa0# 18 csa1# csa2# csa4# csa3# gnd 19 srasa# csa5# mab0# mab1# reserved 20 reserved reserved mab2# reserved mab3# 21 reserved mab4# gnd reserved mab6# 22 reserved reserved mab5# reserved mab7# 23 mab8# reserved reserved mab9# mab10 24 reserved mab11# mab12# reserved dclko 25 mab13 v_3 gnd cke0 dclkrd 26 cke1 mid2 cke3 cke4 gnd 27 cke5 cke2 mid3 g_cpu_stp# vrchgng# 28 reserved g_lo/hi# dqma2 dclkwr gnd 29 gnd vtt reserved fs_preq# dqma3 30 fs_reset# v_3 md26 gnd md25 31 fs_prdy# gnd md58 md57 md60 32 g_sus_stat1# smclk tdo tclk ferr# 33 reserved smdat tdi tms ignne#
pentium ? ii processor C low-power module 20 datasheet 34 reserved fqs reserved trst# atf_int# 35 reserved v_5 v_3s v_3s v_3s 36 v_cpupu v_5 v_3s v_3s v_3s 37 v_clk v_5 v_3s v_3s v_3s 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc table 12. connector pin assignments, row f through row k (sheet 1 of 2) pin# row f row g row h row j row k 1 greq# gnd pipe# sba3 gnd 2 st0 st1 sba1 sbstb gclki 3 ggnt# st2 sba2 gnd gclko 4 gad13 gstop# gad16 gad20 gad23 5 gad12 gpar gad18 gad17 gc/be3# 6 gad10 gad15 gframe# gnd gad22 7 gad11 gc/be1# gtrdy# gc/be2# gad21 8 gad9 gad14 gdevsel# girdy# gad19 9 gnd vccagp gnd vccagp gad28 10 ad0 ad4 ad2 ad3 ad1 11 gnd c/be0# ad6 gnd ad5 12 vccagp ad10 ad7 ad8 ad9 13 mecc1 ad13 gnd ad12 ad11 14 serr# par ad15 c/be1# ad14 15 ad16 trdy# stop# devsel# plock# 16 ad19 gnd ad17 gnd ad18 17 ad23 ad30 ad24 c/be2# ad21 18 ad27 ad22 c/be3# ad26 pclk 19 pci_rst# gnd ad20 ad28 gnd 20 reserved phold# ad31 ad29 ad25 21 irdy# frame# gnd req1# req0# 22 gnd gnt2# req2# req3# gnt3# 23 gnt1# gnt4# gnt0# req4# gnd 24 gnd phlda# gnd v_3 md59 25 dqma6 mecc7 md50 md51 md54 26 mecc2 md48 md18 md52 md24 27 dqma7 md16 md19 gnd md23 table 11. connector pin assignments, row a through row e (sheet 2 of 2) pin# row a row b row c row d row e
pentium ? ii processor C low-power module datasheet 21 3.3 pin and pad assignments the module connector is a surface mount, 1.27 mm pitch bga style, 400-pin connector. there are currently three unique mating connector receptacles that are available for the module from berg electronics (part number 74219-002). figure 2 shows the connector pad assignments for the manufacturers system electronics. this footprint is viewed from the secondary side of the processor module (the side of the printed circuit board on which the 400-pin connector is soldered). 28 mecc6 md17 md21 md53 md55 29 mecc3 md49 md20 md22 md56 30 md27 md28 gnd md62 md63 31 gnd md29 md61 md30 md31 32 smi# intr vr_on gnd gnd 33 nmi sus_stat1# vr_pwrgd gnd hclk0 34 a20m# stpclk# init# gnd gnd 35 v_3 v_3 v_3 gnd hclk1 36 v_3 v_3 v_3 gnd gnd 37 v_3 v_3 v_3 v_3 v_3 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc table 12. connector pin assignments, row f through row k (sheet 2 of 2) pin# row f row g row h row j row k
pentium ? ii processor C low-power module 22 datasheet table 13 summarizes some of the more critical specifications for the connector. figure 2. 400-pin connector footprint pad numbers, module secondary side 400-pin connector oem pad assi g nments (viewed from secondary side) k a 1 40 table 13. connector specifications parameter condition specification material contact copper alloy housing thermo plastic molded compound: lcp electrical current 0.5 a voltage 50 v ac insulation resistance 100 m w min. @ 500 vdc termination resistance 20m w max. @ 20mv open circuit with 10ma capacitance 5 pf max. per contact mechanical mating cycles 50 cycles connector mating force 0.9 n (90 gf) max. per contact contact un-mating force 0.1 n (10 gf) min. per contact
pentium ? ii processor C low-power module datasheet 23 4.0 functional description 4.1 low-power module the pentium ii processor C low-power module supports the pentium ii processor C low power core running 266/66 mhz with 32 kbyte l1 code and data cache sizes. 4.2 l2 cache the processor cores internal cache is complimented with a second-level cache using a high- performance pipeline burst sram which uses a dedicated high speed bus into the processor core. the l2 cache can support 512 mbytes of system memory, while the maximum amount of cacheable system memory supported by the 443bx host bridge/controller is 256 mbytes with 16 mbit drams. (the system controller can support up to 1 gbytes of system memory using 64-mbit technology.) the module has two 100-pin tqfp footprints for 512 kbyte direct-mapped write- back l2 cache. the module supports the stop clock mode of power management for the l2 srams. in this mode, the clock signals to the synchronous srams are stopped or parked in a low-power state. 4.3 443bx host bridge/controller intels 443bx host bridge/controller is a highly integrated device that combines the bus controller, the dram controller, and the pci bus controller into one component. the 443bx host bridge has multiple power management features for low-power systems: ? clkrun# is a feature that enables controlling of the pci clock on or off ? 443bx host bridge suspend modes include suspend-to-ram (str), suspend-to-disk (std) and powered-on-suspend (pos) ? system management ram (smram) power management modes include compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1 mbyte. to minimize power consumption while the system is idle, the internal 443bx host bridge clock is turned off (gated off) when there is no processor and pci activity. the module supports only the 443bx host bridge/controller features in mobile compatible or legacy mode. refer to the intel 440bx agpset: 82443bx host bridge/controller datasheet (order number 290633) for complete details.
pentium ? ii processor C low-power module 24 datasheet 4.3.1 memory organization the complete memory interface of the 443bx host bridge/controller is available at the modules connector; all of the 443bx standard mode memory configurations and modes of operation are supported on the signaling interface. this allows the memory interface to support the following: ? one set of memory control signals, sufficient to support up to three so_dimm sockets and six banks of sdram at 66 mhz ? one cke signal for each banks key memory features not supported by the 443bx host bridge/controller standard mode are: ? support for eight banks of memory ? second set of memory address lines (maa[13:0]) ? 100 mhz sdram (and front side bus) dram technologies supported by 443bx host bridge/controller include extended data out (edo) and sdram. these memory types may not be mixed in the system. in other words, all dram in all rows (ras[5:0]#) must be of the same technology. the 443bx host bridge/controller targets 60 ns edo drams. and 66 mhz sdrams. the modules clocking architecture supports the use of sdram. due to the tight timing requirements of 66-mhz sdram clocks, the clocking mode for sdram or system manufacturer custom memory configurations allows all host and sdram clocks to be generated from the same clocking architecture on the oems system electronics. for complete details about using sdram memory, and for trace length guidelines, see the pentium ? ii processor C low power module at 266 mhz C 66 mhz sdram dimm routing guidelines (order number 273230). for details on memory device support, organization, size and addressing, refer to the intel 440bx agpset: 82443bx host bridge/controller datasheet (order number 290633). 4.3.2 reset strap options the 443bx host bridge/controller has several strap options on the memory address bus which define the behavior of the device after reset. for the module, several of these strap options are implemented on the module. other straps are allowed to override the default settings. table 14 shows the various straps and how they are handled by the module. table 14. configuration straps for the 443bx host bridge/controller signal function module default setting optional override on system electronics mab[12]# host frequency select no strap. (66 mhz default) none ma[11]# in order queue depth no strap. (maximum queue depth is set (i.e., 8)) none ma[10] quick start select strapped high on the module for quick start mode. none ma[9]# agp disable no strap. agp is enabled pull up this signal to disable agp interface. ma[7]# mm config no strap. standard mode. none ma[6]# host bus buffer mode select strapped high on the module for fsb buffers. none
pentium ? ii processor C low-power module datasheet 25 4.3.3 pci interface the 443bx host bridge/controller is compliant with the pci 2.1 specification, which improves the worst-case pci bus access latency from earlier pci specifications. the complete pci interface of the 443bx host bridge/controller is available at the connector. the 443bx host bridge/controller supports the pci clockrun protocol for pci bus power management. in this protocol, pci devices assert the clkrun# open-drain signal when they require the use of the pci interface. the 443bx host bridge/controller is responsible for arbitrating the pci bus. since the module is configured in mobile compatible or legacy mode, the 443bx host bridge/controller can support only up to five pci bus masters. there are five pci request/grant pairs, req[4:0]# and gnt[4:0]#, available on the connector to the manufacturers system electronics. the pci interface on the module is 3.3 v only. 5 v pci devices are not supported, specifically all devices which drive outputs to a 5 v nominal voh level. the 443bx host bridge/controller supports only mechanism #1 for accessing pci configuration space, as detailed in the pci specification. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 443bx host bridge is always device #0; ad11 will never be asserted during pci configuration cycles as an idsel. ad12 is reserved by the 443bx for the agp bus. thus, ad13 is the first available address line usable as an idsel. ad18 is recommended to be used by the piix4e southbridge. 4.3.4 agp interface the 443bx host bridge/controller is compliant with the agp rev. 1.0 specification, which supports only an asynchronous agp interface coupling to the 443bx core frequency. the agp interface can reach a theoretical ~500 mbytes/s transfer rate (i.e., using agp 2x/133 devices). the actual bandwidth will be limited by the capability of the 443bx memory subsystem. 4.4 electrical requirements the following section provides information on the dc requirements for the module.
pentium ? ii processor C low-power module 26 datasheet 4.4.1 dc requirements refer to table 15 for power supply design criteria to ensure compliance with the modules dc power requirements. table 15. power supply design specifications symbol parameter min nom max unit notes 1 v dc dc input voltage 5.0 12.0 21.0 v i dc 1,2 dc input current 0.1 0.9 3.5 a i dc-surge maximum surge current for v dc 17.3 a idc-leakage 3 typical leakage current for v dc 4.0 a (at 25 c) v 5 power managed 5v voltage supply 4.75 5.0 5.25 v i 5 power managed 5v current 17 32 60 ma i 5-surge maximum surge current for v 5 0.6 a i 5-leakage typical leakage current for v 5 1.0 a v 3 power managed 3.3v voltage supply 3.135 3.3 3.465 v i 3 power managed 3.3v current 0.8 1.2 2.0 a i 3-surge maximum surge current for v 3 2.8 a i 3-leakage typical leakage current for v 3 1.1 ma v cpupu processor i/o ring voltage 2.375 2.5 2.625 v 0.125 i cpupu 4 processor i/o ring current 0 10 20 ma v clk processor clock rail voltage 2.375 2.5 2.625 v 0.125 i clk 5 processor clock rail current 24.0 35.0 80 ma notes: 1. v_dc is set for 12 v in order to determine typical v_dc current. 2. v_dc is set for 5 v in order to determine maximum v_dc current. 3. leakage current that can be expected when vr_on is deactivated and v_dc is still applied. 4. these values are system dependent.
pentium ? ii processor C low-power module datasheet 27 4.4.2 ac requirements please refer to table 16 for module ac timing requirements for bclk. bclk system timing is specified in terms of signal quality. the waveform of figure 6 describes a typical system bus clock as seen at the processor core pin. table 16. module ac specifications (bclk) at the processor core pins t# parameter min nom max unit figure notes 1,2,3 system bus frequency 66.67 mhz all processor core frequencies 4 t1: bclk period 15. ns 4, 5, 6 t2: bclk period stability 250 ps 6, 7, 8, 9 t3: bclk high time 5.3 ns @>1.765 v 6 t4: bclk low time 5.3 ns @<0.5 v 6 t5: bclk rise time 0.175 0.875 ns (0.9 v-1.6 v) 6,9 t6: bclk fall time 0.175 0.875 ns (1.6 vC0.9 v) 6,9 notes: 1. unless otherwise noted, all specifications in this table apply to all modules. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 1.25 v at the processor core pin. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor core pins. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25 v at the processor core pin. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25 v at the processor core pins. 4. the internal core clock frequency is derived from the system bus clock. the system bus clock to core clock ratio is determined during initialization as described and is predetermined by the module. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. see the ck97 clock synthesizer/driver specification for further information. 6. this specification applies to the pentium ii processor system bus frequency of 66 mhz. 7. due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pf. this should be measured on the rising edges of adjacent bclks crossing 1.25 v at the processor core pin. the jitter present must be accounted for as a component of bclk timing skew between devices. 8. the clock drivers closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the C20 db attenuation point, as measured into a 10 to 20 pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the ckdm66-m clock synthesizer/driver specification for further details. 9. not 100% tested. specified by design characterization as a clock driver requirement.
pentium ? ii processor C low-power module 28 datasheet 4.4.2.1 system bus clock (bclk) signal quality specifications and measurement guidelines table 17 describes the signal quality specifications at the processor core for the module system bus clock (bclk) signal. figure 3 describes the signal quality waveform for the system bus clock at the processor core pins. table 17. bclk signal quality specifications for simulation at the processor core t# parameter min nom max unit figure notes 1 v1: bclk v il 0.5 v 3 v2: bclk v ih 1.765 v 3 2 v3: v in absolute voltage range C0.8 3.3 v 3 2 v4: rising edge ringback 1.765 v 3 3, 4 v5: falling edge ringback 0.5 v 3 4 notes: 1. unless otherwise noted, all specifications in this table apply to all modules. 2. this is the pentium ii processor system bus clock overshoot and undershoot specification for 66-mhz system bus operation. 3. clock signal must be monotonic from +0.5 v to +1.765 v. 4. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. this specification is an absolute value. figure 3. bclk, tck, picclk generic clock waveform at the processor core pins v2 v1 v3 v3 t3 v5 v4 t6 t4 t5
pentium ? ii processor C low-power module datasheet 29 4.5 module signal termination system design requirements for signal termination for the module have been split between the processor module and the system electronics. the system designer is responsible for ensuring proper termination on the signals. 4.6 processor core voltage regulation the modules dc voltage regulator (dc/dc converter) is designed to support the core voltage and i/o ring voltage for current and future processors. the dc voltage regulator provides the appropriate processor core voltage, the processor sideband signal pull-up voltage, and the i/o voltage for the components on the processor core backside bus. of these voltages, only the processor sideband pull-up voltage (v_cpupu) is delivered to the system electronics. the module supports an input dc voltage range of 5 v - 21 v from the system battery, or power supply. 4.6.1 voltage regulator efficiency there are three voltage regulators on the module. these voltage regulators generate the core voltage used by the cpu, the voltage for the backside bus, and the voltage for the cpu i/o ring voltage. the core voltage regulator provides the required current from the v_dc (battery or a/c voltage adapter) supply. its relative efficiencies are shown in table 18. the backside bus i/o and cpu i/o ring voltage regulators tap the v_3 plane and are about 85 percent efficient at typical loads. table 18. typical voltage regulator efficiency icore, a 3 v_dc, v i_dc, a 2 efficiency 1 v_dc, v i_dc 2 efficiency 1 1 5.00 0.394 83% 18.00 0.135 68% 2 5.00 0.752 88% 18.00 0.233 80% 3 5.00 1.212 82% 18.00 0.340 82% 4 5.00 1.506 88% 18.00 0.451 82% 5 5.00 1.921 86% 18.00 0.561 82% 6 5.00 2.290 86% 18.00 0.674 82% 7 5.00 2.683 85% 18.00 0.790 81% 1 12.00 0.186 74% 21.00 0.129 62% 2 12.00 0.335 83% 21.00 0.215 74% 3 12.00 0.491 85% 21.00 0.304 79% 4 12.00 0.652 85% 21.00 0.396 81% 5 12.00 0.816 85% 21.00 0.493 81% 6 12.00 0.980 84% 21.00 0.592 80% 7 12.00 1.149 83% 21.00 0.692 80% notes: 1. these efficiencies will change with future voltage regulators that accommodate wider ranges of input voltages. 2. with v_dc applied and the voltage regulator off, typical leakage is 0.3 ma with a maximum of 0.7 ma. 3. icore indicates the processor core current being drawn during test and measurement.
pentium ? ii processor C low-power module 30 datasheet 4.6.2 voltage regulator control the vr_on pin on the connector allows a digital signal (3.3 v, 5 v safe) to control the voltage regulator. the system manufacturer can use this signal to turn the modules voltage regulator on or off. vr_on should be controlled as a function of the same digital control signal (susb#) used to control the systems switched 5 v/3.3 v power planes. the piix4e southbridge defines suspend b as the power management state in which power is physically removed from the processor, l2 cache, 443bx host bridge/controller, and voltage regulator. in this state, the susb# pin on the piix4e controls these power planes. caution: vr_on should switch high only when the following conditions are met; v_5(s) 3 4.5 v, and v_dc 3 4.75 v. turning on vr_on prior to meeting these conditions will severely damage the module. see figure 4 on page 31 for the proper timing sequencing. 4.6.2.1 voltage signal definition and sequencing table 19. voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics dc voltage driven from the power supply and is required to be between 5v and 21v dc. v_dc powers the modules dc-to-dc converter for processor core and i/o voltages. the module cannot be hot inserted or removed while v_dc is powered on. v_3 system electronics v_3 is supplied by the system electronics for the 443bx. v_5 system electronics v_5 is supplied by the system electronics for the 443bxs 5v reference voltage and modules voltage regulator. v_3s system electronics v_3s is supplied by the system electronics for the l2 cache devices. each must be powered off during system str and std states. vr_on system electronics enables the modules voltage regulator circuit. when driven active high (3.3v) the voltage regulator circuit on the module is activated. the signal driving vr_on should be a digital signal with a rise/fall time of less than or equal to 1 m s. v_core (also used as host bus gtl+ termination voltage vtt) module only; not on module interface. a result of vr_on being asserted, v_core is an output of the dc-dc regulator on the module and is driven to the core voltage of the processor. it is also used as the host bus gtl+ termination voltage, known as vtt. v_bsb_io module only; not on module interface. v_bsb_io is 1.8v. the system electronics uses this voltage to power the l2 cache-to-processor interface circuitry. vr_pwrgd module upon sampling the voltage level of v_core for the processor, minus tolerances for ripple, vr_pwrgd is driven active high (3.3 v) for the system electronics to sample prior to providing pwrok to the piix4e. if vr_pwrgd is not sampled active within 1 second of the assertion of vr_on the system electronics should deassert vr_on. v_cpupu module v_cpupu is 2.5 v. the system electronics uses this voltage to power the piix4e-to-processor interface circuitry. v_clk module v_clk is 2.5 v. the system electronics uses this voltage to power the hclk_(0:1) drivers for the processor clock.
pentium ? ii processor C low-power module datasheet 31 figure 4 details the sequencing of signals and voltage planes required for normal operation of the module. the module provides the vr_pwrgd signal, which indicates that the voltage regulator power is operating at a stable voltage level. the system manufacturer should use this signal on the system electronics to control power inputs and to gate pwrok to the piix4e southbridge. note: the vr_on signal should be driven by a digital signal with a rise/fall time of less than or equal to 1 s and signaling voltage levels that meet the requirement of vil(max)=0.4v and vih(min)=3.0 v. figure 4. power on sequence timing power sequence timing v_dc 1. pwrok on i/o board should be active on when vr_pwrgd is active and v_3s is good. 2. cpu_rst from i/o board should be active for a minimum of 6 ms after pwrok is active and pll_stp# and cpu_stp# are inactive. note that pll_stp# is an and condition of rsmrst# and susb# on the piix4. 3. v_dc >= 4.7v, v_5>=4.5v, v_3s>=3.0v. 4. v_cpupu and v_clk are generated on the intel mobile module. 5. this is the 5v power supplied to thep rocessor module connector. this should be the first 5v plane to power up. v_3 v_5 vr_pwrgd v_3s vr_on 0 ms min 0 ms min 0 ms min 6 ms max note 3 v_cpupu/ v_clk see note 5
pentium ? ii processor C low-power module 32 datasheet 4.6.3 power planes: bulk capacitance requirements in order to provide adequate filtering and in-rush current protection for any system design, bulk capacitance is required. a small amount of bulk capacitance is supplied on the module, however, in order to achieve proper filtering additional capacitance should be placed on the system electronics. table 20 details the bulk capacitance requirements for the system electronics when using the module. 4.6.4 surge current study surge current analysis was performed on a typical system power supply to determine the maximum amount of surge current that the module is capable of handling. this information was then used to develop the module system i/o bulk capacitance requirements (table 20). this section provides the results of this study. figure 5 shows an electrical model used when analyzing instantaneous power-on conditions. the following analysis is provided as a worst case analysis. depending on the system electronics design, different impedances may be seen yielding different results. the oem should perform a thorough analysis to understand the implications of surge current on their system. as previously stated, the following study was performed in a worst-case situation with no bulk capacitance on the v_dc line on the system electronics. given that, the module has two 4.7 f with an esr of 0.3 w each. the module connector is approximately 30 m w of series resistance for a total series resistance of 0.33 w . if the user powers the system with the a/c adapter (18 v), the amount of surge current seen by the capacitors on the module would be greater than 50 amps! figure 6 illustrates the results of this situation with a spice simulation. table 20. capacitance requirement per power plane power plane capacitance require- ments esr ripple current rating v_dc 100 f, 0.1 f, 0.01 f 1 20 m w 1-3.5 amp 3 20% tolerance @ 35 v v_5 100 f, 0.1 f, 0.01 f 1 100 m w 1 amp 20% tolerance @ 10 v v_3 470 f, 0.1 f, 0.01 f 1 100 m w 1 amp 20% tolerance @ 6 v v_3s 100 f, 0.1 f, 0.01 f 1 100 m w 1 amp 20% tolerance @ 6 v vcc_agp 22 f, 0.1 f, 0.01 f 1 100 m w 1 amp 20% tolerance @ 6 v v_cpupu 2.2 f, 8200 pf 2 n/a n/a 20% tolerance @ 6 v v_clk 10 f, 8200 pf 2 n/a n/a 20% tolerance @ 6 v notes: 1. placement of above capacitance requirements should be located near the module connector. 2. v_clk filtering should be located next to the system clock synthesizer. 3. ripple current specification depends on v_dc input. for 5.0 v v_dc, a 3.5 a device is required. for v_dc at 18 v or higher, 1 a is sufficient.
pentium ? ii processor C low-power module datasheet 33 due to the stringent component height requirements ( 4mm) of the module, tantalum capacitors must be used as input bulk capacitance in the voltage regulator circuit. because of tantalum capacitors susceptibility to high in-rush current, special care must be taken to soften the initial rush of current applied to these capacitors. one way to soften the in-rush current and provide over voltage/over current protection is to ramp up v_dc slowly using a circuit similar to the one shown in figure 7. figure 5. instantaneous in-rush current model figure 6. instantaneous in-rush current
pentium ? ii processor C low-power module 34 datasheet 4.6.4.1 slew-rate control: circuit description in figure 8, pwr is the voltage generated by applying the ac adaptor or battery. m1 is a low rds(on) p-channel mosfet such as a siliconix si4435dy. when the voltage on pwr is applied and increased to over 4.75 v, the under_voltage_lockout circuit allows r4 to pull up the gate of m3 to start a turn-on sequence. m3 pulls its drain toward ground forcing current to flow through r2. m1 will not start to source any current until after t_delay with t_delay defined as: the manufacturers vgs_max specification of 20 v must never be exceeded. however, vgs_max must be high enough to keep the rds (on) of the device as low as possible. after the initial t_delay, m1 will begin to source current and v_dc will start to ramp up. the ramp up time, t_ramp, is defined as: maximum current during the voltage ramping is: with the circuit shown in figure 10, t_delay = 5.53 ms, t_tran = 14.0 ms and i_max = 146 ma. figure 7. over current protection circuit t_delay . . r2 c9 ln 1 vt vpwr vgs_max vgs_max . r16 r16 r2 vpwr t_ramp . . r2 c9 ln 1 vsat vgs_max t_delay i . ctotal vpwr t_ramp
pentium ? ii processor C low-power module datasheet 35 figure 8 shows a spice simulation of the circuit in figure 10. to increase the reliability of tantalum capacitors, use a slew rate control circuit described in figure 7 and voltage-derate the capacitor about 50 percent. that is, for a maximum input voltage of 18 v, use a 35 v capacitor with low esr with high ripple current capability. on the base board, place five 22 f/35 v capacitors directly at the v_dc pins of the processor module connector. an acceptable capacitor for this application would be the component from avx: tpse226k035r0300. one more issue that must be raised here is that the slew rate control circuit should be applied to every input power source to the system v_dc to provide the most protection. if all power sources (i.e., battery or batteries, ac adaptor, etc.) are ored together at the pwr node, there is still a potential problem. for example, if a 3x3 li-ion battery pack is powering the system (12 v at pwr), and the ac adaptor (18 v) is plugged into the system, it will immediately source current to the pwr node and v_dc rapidly. this is because the slew rate control is already on. therefore, the slew rate control must be applied to every input power source to provide the most protection. also shown in figure 10 are under and over voltage and over-current protection circuits that can be used to increase the protection level for the module. figure 8. spice simulation using in rush protection
pentium ? ii processor C low-power module 36 datasheet 4.6.4.2 under-voltage lockout: circuit description the circuit shown in figure 8 provides an under-voltage protection and locks out the applied voltage to the module to prevent an accidental turn-on at low voltage. the output of this circuit, pin 1 of the lm339 comparator, is an open-collector output. it is low when the applied voltage at pwr is less than 4.75 v. this voltage can be calculated with the following equation with the voltage across d7 as 2.5 v. (d7 is a 2.5-v reference generator.) 4.6.4.3 over voltage lockout: circuit description the module is specified to operate with a maximum input voltage of 21 v. this circuit locks out the input voltage if it exceeds the maximum 21 v. the output of this circuit, pin 14 of the lm339 comparator, is an open-collector output. it is low when the applied voltage at pwr is more than 21 v. this voltage can be calculated with the following equation: 4.6.4.4 over current protection: circuit description figure 8 shows that the circuit detects an over-current condition and cuts off the input voltage applied to the module. this circuit has two different current limit trip points. this takes into account the different maximum current drain by the module at different input voltages (i.e., whether the ac adaptor is plugged in or not.) assuming the ac adapter voltage is 18 v and the battery is a 3x3 li-ion configuration with a minimum voltage of 7.5 v, the maximum current for the above circuit can be calculated using the following equation: with ac adaptor: i_wadaptor = 0.989 amp i_woadaptor = 2.375 amp v_uv_lockout . vref 1 r17 . r18 r25 r18 r25 = v_uv_lockout 4.757 volt v_ov_lockout . . vref r26 r26 r27 1 r24 r23 = v_ov_lockout 20.998 volt i_wadaptor . vref vbe_q1 r14 r13 r1 i_woadaptor . vref vbe_q1 . r14 r33 r14 r33 r13 r1
pentium ? ii processor C low-power module datasheet 37 4.7 active thermal feedback table 21 identifies the address allocated for the system management bus (smbus) thermal sensor used on the module. 4.8 power management 4.8.1 clock control architecture the processor clock control architecture (figure 9) has been optimized for leading edge deep green system designs. the auto halt state provides a low power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a very low power, low exit latency clock state that can be used for hardware controlled idle computer states. the deep sleep state provides an extremely low power state that can be used for power-on suspend computer states, which is an alternative to shutting off the processors power. compared to the pentium processor exit latency of 1 ms, the exit latency of the deep sleep state has been reduced to 30 s in the pentium ii processor C low power. the stop grant and sleep states shown in figure 9 are intended for use in deep green desktop and server systemsnot in applied computing systems. performing state transitions not shown in figure 9 is neither recommended nor supported. the clock control architecture consists of seven different clock states: normal, stop grant, auto halt, quick start, halt/grant snoop, sleep and deep sleep states. the stop grant and quick start clock states are mutually exclusive, i.e., a strapping option on pin a15# chooses which state is entered when the stpclk# signal is asserted. the quick start state is enabled by strapping the a15# pin to ground at reset; otherwise, asserting the stpclk# signal puts the processor into the stop grant state. the stop grant state has a higher power level than the quick start state and is designed for smp platforms. the quick start state has a much lower power level, but it can only be used in uniprocessor platforms. table 24 provides clock state characteristics (power numbers based on estimates for a pentium ii processor C low power running at 266 mhz), which are described in detail in the following sections. table 21. thermal sensor smbus address function fixed address ad bits (6:4) selectable address ad bits (3:0) thermal sensor 100 1110 reserved 010 1010 reserved 010 1011 note: the thermal sensor used is compliant with smbus addressing. please refer to the pentium ? ii processor thermal sensor interface specification . table 22. new pins in the pentium ? ii processor C low power pin name type description smbalert# o thermal sensor attention signal. smbclk i/o smbus clock signal. refer to the system management bus specification for descriptions and specifications of the three smbus signals. smbdata i/o smbus data signal. refer to the system management bus specification for descriptions and specifications of the three smbus signals.
pentium ? ii processor C low-power module 38 datasheet figure 9. pentium ? ii processor C low power clock control states note: the shaded states are features of the pentium ? ii processor C low power but are not implemented by the module. the module never enters the shaded states. halt/grant snoop normal state hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qss and stop grant bus cycle snoop occurs snoop serviced stpclk# and qss and stop grant bus cycle (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qss and stop grant bus cycle hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qss and stop grant bus cycle !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qss bclk stopped bclk on and qss halt break - binit#, flush#, smi#, nmi, intr, init#, reset#, a20m# stop break - binit#, flush#, reset# qss - quick start strapping option hs - processor halt state hlt - hlt instruction executed
pentium ? ii processor C low-power module datasheet 39 4.8.2 normal state the normal state of the processor is the normal operating mode where the processors internal clock is running and the processor is actively executing instructions. 4.8.3 auto halt state this is a low power mode entered by the processor through the execution of the hlt instruction. the power level of this mode is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush# or smi#). asserting the stpclk# signal while in the auto halt state causes the processor to transition to the stop grant or quick start state, where a stop grant acknowledge bus cycle is issued. by deasserting stpclk#, system logic can return the processor to the auto halt state without issuing a new halt bus cycle. the smi# interrupt is recognized in the auto halt state. the return from the system management interrupt (smi) handler can be to either the normal state or the auto halt state. see the intel architecture software developers manual, volume iii: system programmers guide, for more information. no halt bus cycle is issued when returning to the auto halt state from smm. the flush# signal is serviced in the auto halt state. after the on-chip and off-chip caches have been flushed, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# pin are recognized while in the auto halt state. table 23. processor clock state characteristics clock state exit latency power snooping? system uses normal n/a varies yes normal program execution auto halt approximately 10 bus clocks 1.2 w yes s/w controlled entry idle mode stop grant 10 bus clocks 1.2 w yes h/w controlled entry/exit throttling quick start through snoop , to halt/grant snoop state: immediate through stpclk# , to normal state: 10 bus clocks 0.5 w yes h/w controlled entry/exit throttling halt/ grant snoop a few bus clocks after the end of snoop activity. not specified yes supports snooping in the low power states sleep to stop grant state 10 bus clocks 0.5 w no h/w controlled entry/exit desktop idle mode support deep sleep 30 s 100 mw no h/w controlled entry/exit powered-on suspend support
pentium ? ii processor C low-power module 40 datasheet 4.8.4 stop grant state the processor enters this mode with the assertion of the stpclk# signal when it is configured for stop grant state (via the a15# strapping option). the processor is still able to respond to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the de-assertion of the stpclk# signal, or the occurrence of a stop break event (a binit#, flush# or reset# assertion). while in the stop grant state, smi#, init# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been deasserted. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip and off-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. 4.8.4.1 quick start state this is a mode entered by the processor with the assertion of the stpclk# signal when it is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the system bus priority device. because of its snooping behavior, quick start can only be used in a uniprocessor (up) configuration. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupt, servicing snoop transactions from symmetric bus masters or responding to flush# or binit# assertions. while the processor is in the quick start state, it will not respond properly to any input signal other than stpclk#, reset# or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. the thermal sensor will respond normally to smbus transactions when the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. asserting the slp# signal when the processor is configured for quick start will result in unpredictable behavior and is not recommended.
pentium ? ii processor C low-power module datasheet 41 4.8.5 halt/grant snoop state the processor will respond to snoop transactions on the system bus while in the auto halt, stop grant or quick start state. when a snoop transaction is presented on the system bus the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop on the system bus has been serviced and the system bus is quiet. after the snoop has been serviced, the processor will return to the previous auto halt, stop grant or quick start state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state, except for those signal transitions that are required to perform the snoop. 4.8.6 sleep state the sleep state is a very low power state in which the processor maintains its context and the phase-locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop grant state, the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# pin is not recognized in the normal or auto halt states. the processor can be reset by the reset# pin while in the sleep state. if reset# is driven active while the processor is in the sleep state then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly executes the reset sequence. input signals (other than reset#) may not change while the processor is in the sleep state or transitioning into or out of the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. the thermal sensor will respond normally to smbus transactions when the processor is in the sleep state. while in the sleep state, the processor is capable of entering its lowest power state, the deep sleep state, by removing the processors input clock. picclk may be removed in the sleep state. 4.8.7 deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. the deep sleep state is entered by stopping the bclk input to the processor, while it is in the sleep or quick start state. for proper operation, the bclk input should be stopped in the low state. to re-enter either the sleep or quick start state from the deep sleep state, the bclk input must be restarted. the processor will return to the sleep or quick start state, as appropriate, after 30 ms. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on when transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior. the thermal sensor will respond normally to smbus transactions when the processor is in the deep sleep state.
pentium ? ii processor C low-power module 42 datasheet 4.8.8 currently supported clock states table 24 shows the low-power clock states supported by the pentium ii processor family product line. 4.8.9 operating system implications of the quick start and sleep states there are a number of architectural features of the pentium ii processor C low power that are not available when the quick start state is enabled or do not function in the quick start or sleep state as they do in the stop grant state. these features are part of the apic, time-stamp counter and performance monitor counters. the local apic timer does not behave properly when the processor is in the quick start or sleep state. there is no guarantee that the local apic timer will count down in the quick start or sleep state. if the timer counts down to zero when the processor is in or about to enter the quick start or sleep state, the processors behavior will be unpredictable. inter-processor interrupts (ipis) should not be used in pentium ii processor C low power systems. if software generates an ipi just before the processor enters the quick start or sleep state, then a message on the apic bus will be generated. this would violate the requirement that no input signals toggle in the quick start or sleep state. any software-generated ipi in a pentium ii processor C low power system (uniprocessor system) will always result in an error. the time-stamp counter and the performance monitor counters are not guaranteed to count in the quick start or sleep states. if software sets the apic interrupt enable bit of either of the performance counters, then the resulting behavior will be unpredictable. 4.9 typical pos/str power the module supports both power on suspend (pos) and suspend to ram (str) features. typical power during these states are: these are average values of measurement on several typical modules and are guidelines only. table 24. low-power clock states supported by processor processor clock state stop grant auto halt quick start sleep deep sleep pentium ? pro processor x x pentium ii processor x x x x pentium ii processor C low power xxxxx pentium ii processor C low-power module xx x state module power pos 910mw str 3mw
pentium ? ii processor C low-power module datasheet 43 5.0 mechanical requirements 5.1 module dimensions this section provides the physical dimensions for the module. 5.1.1 board area figure 10 shows the board dimensions and the connector orientation for the module. figure 10. low-power module board dimensions
pentium ? ii processor C low-power module 44 datasheet 5.1.2 module pin 1 location figure 11 shows the location of pin 1 of the 400-pin connector as referenced to the adjacent mounting hole. figure 11. low-power module board dimensions connector pin 1 orientation figure 12. pcb board thickness min: 0.90mm max: 1.10mm processor module printed circuit board
pentium ? ii processor C low-power module datasheet 45 5.1.3 printed circuit board thickness figure 12 shows the module profile and the associated minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for different pcb technologies to be used with current and future modules. note: the system manufacturer must ensure that the mechanical restraining method and/or system-level emi contacts are able to support this range of pcb thickness, to ensure compatibility with future modules. 5.1.4 height restrictions figure 13 shows the module mechanical stackup and associated component clearance requirements. the system manufacturer establishes the board-to-board clearance between the module and the system electronics by selecting one of three possible mating connectors. the mating connectors provide board-to-board clearances (distance underneath the module) of 4 mm, 6 mm or 8 mm. with these three options, the system manufacturer has reasonable flexibility in choosing components on the system electronics that are between the two boards. the connector receptacles are available from berg electronics (part number 74219-002). note: the module top side component clearance is referenced from the bottom of the pcb, so it is independent of the pcb thickness. figure 13. module mechanical drawing
pentium ? ii processor C low-power module 46 datasheet 5.2 thermal transfer plate the module provides a thermal transfer plate, or ttp, connected to the processor in a standard position called the thermal attach point (see figure 14 and figure 15 for exact dimensions). the thermal attach point is a fixed location relative to the mounting holes and other physical datum on the module. the system manufacturer can use both a heat pipe and a heat spreader plate in contact with the thermal attach point to transfer heat through the system or a thermal solution of their choice. the ttp thermal resistance as measured between the processor core to the top of the ttp is less than 1 c per watt. the thermal transfer plate is physically mounted to the module, and may be different from one generation of module to the next. the following figures detail the mechanical dimensions of the thermal transfer plate used on the module, and the conceptual relationship between the circuit board thermal transfer plate, and thermal attach point. figure 14. thermal transfer plate
pentium ? ii processor C low-power module datasheet 47 5.3 module physical support figure 16 shows the module standoff support hole patterns and the board edge clearance around the perimeter of the module. these hole locations and board edge clearances will remain fixed for all modules. the hole patterns and board edge clearance lets the system manufacturer develop several methods for mechanically supporting the module within a system. 5.3.1 module mounting requirements three mounting holes are available to the system oem for securing the module to the system base or the system electronics. see figure 10 for mounting hole locations. it is strongly recommended that the designer use mounting screws through all three of the mounting holes to ensure long term reliability of the mechanical and emi integrity of the system. to interface to the modules thermal transfer plate (ttp), it is recommended that the exact dimensions shown in figure 14 for the oem thermal interface block be used. these dimensions provide maximum contact area to the ttp while ensuring that no warpage of the ttp occurs. if warpage occurs due to the use of an improperly-designed interface, or over-tightening of assembly screws, the thermal resistance of the module could be adversely affected. figure 15. thermal transfer plate
pentium ? ii processor C low-power module 48 datasheet when attaching the mating block to the module ttp, material such as a thermal elastomer or thermal grease should be used. this material is designed to reduce the thermal resistance and should be placed between the ttp and the oem mating block. this will improve the overall system thermal efficiency. after the oem has placed the mating thermal transfer plate, it should be secured with 2.0 mm screws using a maximum torque of 1.5 - 2.0 kg*cm (equivalent to 0.147 - 0.197 n*m). the thread length of the 2.00 mm screws should be 2.25 mm gaugeable thread (2.25 mm minimum to 2.80 mm maximum). the board edge clearance includes a 0.762 mm (0.030 in) width emi containment ring around the perimeter of the module. this ring is on each layer of the module pcb and is grounded. on the surface of the module, the metal is exposed for emi shielding purposes. the hole patterns placed on the module also have a plated surrounding ring and one can use a metal standoff to contact the ring for emi shielding purposes. figure 16 shows the dimensions of the emi containment ring and the keepout area. no components are placed on the board in the keepout area. standoffs should be used to provide support for the installed module. the distance from the bottom of the module pcb to the top of the oem system electronics board with the connectors mated is 4.0 mm +0.16 mm / -0.13 mm, however the warpage of the baseboard can vary and should be calculated into the final dimensions of the standoffs used. 5.3.1.1 module weight the weight of the module is 48 g +/- 2 g. figure 16. standoff holes, board edge clearance and emi containment ring
pentium ? ii processor C low-power module datasheet 49 6.0 thermal specifications 7.0 labeling information the module has two means of being tracked. the first means is by labeling information via the intel product tracking code (ptc) and the other is by an oem generated software utility. 7.1 product tracking code the product tracking code label provides module information that is used by intel to determine the assembly level of the module. the ptc label exists on the secondary side of the module and provides the following information: table 25. low-power module power specifications symbol parameter typ max 1 unit notes tdp thermal design power at 266 mhz 13.9 w module (core, northbridge, voltage regulator, & l2 cache) notes: 1. tdp max is a specification of the total power dissipation of the worst-case processor, worst-case northbridge, worst-case l2 cache, and worst-case voltage regulator while executing a worst-case instruction mix under normal operating conditions at nominal voltages. not 100% tested. specified by design/characterization. figure 17. module product tracking information
pentium ? ii processor C low-power module 50 datasheet thirteen letters make up the product tracking code. an example and a definition of each element of the tracking code is shown below. example: pme26605001aa the format is aabcccddeeeff . 7.1.1 module identification bits located on the module are four strapping resistors used to determine the production level of the module. if connected and terminated properly, up to 16 unique module revision levels can be determined. using a software utility generated by the oem, these id bits can be read along with the processor and northbridge stepping ids to provide a complete module manufacturing revision level. 8.0 environmental standards the environmental standards the module are defined in table 26. tracking code definition aa pm - processor module b e - pentium ? ii processor C low power ccc 266 - processor speed dd 05 - cache size, 512 kbyte eee design revision (starts at 001) ff processor revision (starts at aa) table 26. environmental standards parameter condition specification temperature non-operating -40 c to 85 c cycle operating 0 c to 55 c humidity unbiased 85% relative humidity at 55 c voltage v_5 +/- 4% v_3s +/- 4% v_3 +/- 4% shock non-operating half sine, 2 g, 11 ms unpackaged trapezoidal, 50 g, 11 ms packaged inclined impact at 5.7 ft/s packaged half sine, 2 ms at 36" simulated free fall vibration unpackaged 5 hz to 500 hz 2.2 grms random packaged 10 hz to 500 hz 1.0 grms packaged 11,800 impacts 2 hz to 5 hz (low frequency) esd human body model 0 to 2 kv (no detectable err)

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